library verilog;
use verilog.vl_types.all;
entity PIEDecoder is
    generic(
        IDLE            : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi0);
        O               : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi1);
        OO              : vl_logic_vector(0 to 2) := (Hi0, Hi1, Hi0);
        OOL             : vl_logic_vector(0 to 2) := (Hi0, Hi1, Hi1);
        OOLO            : vl_logic_vector(0 to 2) := (Hi1, Hi0, Hi0);
        OOLOL           : vl_logic_vector(0 to 2) := (Hi1, Hi0, Hi1);
        OOLOLL          : vl_logic_vector(0 to 2) := (Hi1, Hi1, Hi0);
        OOLOLLL         : vl_logic_vector(0 to 2) := (Hi1, Hi1, Hi1)
    );
    port(
        Clk             : in     vl_logic;
        Rst             : in     vl_logic;
        Din             : in     vl_logic;
        Dout            : out    vl_logic_vector(7 downto 0);
        D_en            : out    vl_logic;
        F_en            : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of IDLE : constant is 1;
    attribute mti_svvh_generic_type of O : constant is 1;
    attribute mti_svvh_generic_type of OO : constant is 1;
    attribute mti_svvh_generic_type of OOL : constant is 1;
    attribute mti_svvh_generic_type of OOLO : constant is 1;
    attribute mti_svvh_generic_type of OOLOL : constant is 1;
    attribute mti_svvh_generic_type of OOLOLL : constant is 1;
    attribute mti_svvh_generic_type of OOLOLLL : constant is 1;
end PIEDecoder;
